broadcom bcm4360 802.11 (r456083) what cpu

UDP hash table entries: 256 (order: 1, 8192 bytes) TCP: Hash tables configured (established 1024 bind 1024) TCP bind hash table entries: 1024 (order: 1, 8192 bytes)

TCP established hash table entries: 1024 (order: 1, 8192 bytes) SMP: Total of 2 processors activated (3188.32 BogoMIPS).ĭMA: preallocated 256 KiB pool for atomic coherent allocationsįound a ST compatible (Marconix) serial flash with 64 64KB blocks total size 4MBĬCA UART Clock Config: Sel=1 Ovr=1 Div=48 Setting up static identity map for 0xc0011f10 - 0xc0011f44 Sched_clock: 32 bits at 400MHz, resolution 2ns, wraps every 10737msĬalibrating delay loop. MPCORE Global Timer Clock 400000000Hz on IRQ 27 data : 0xc035a000 - 0xc0396808 ( 243 kB)ĬONFIG_RCU_FANOUT set to non-default value of 2Įxternal imprecise Data abort at addr=0x0, fsr=0x1c06 ignored. Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) PID hash table entries: 512 (order: -1, 2048 bytes)ĭentry cache hash table entries: 16384 (order: 4, 65536 bytes) Kernel command line: console=ttyS0,115200 panic=10 root=/dev/mtdblock3 earlyprintk=1 rootfstype=squashfs,jffs2 noinitrd init=/bin/sh PERCPU: Embedded 7 pages/cpu s7040 r8192 d13440 u32768īuilt 1 zonelists in Zone order, mobility grouping on. Memory policy: ECC disabled, Data cache writealloc Linux version 3.10.35-rc1 (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.01 r39555) ) #2136 SMP Sat Mar 29 06:09:ĬPU: ARMv7 Processor revision 0 (ARMv7), cr=10c53c7dĬPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Found a ST compatible (Marconix) serial flash with 32 64KB blocks total size 2MBĬFE version 6.30.163.18 (r377098) based on BBP 1.0.37 for BCM947XX (32bit,SP,)īuild Date: Fri Mar 8 14:09: (C) 2000-2008 Broadcom Corporation.

Broadcom bcm4360 802.11 (r456083) what cpu